1. Field of the Invention
The present invention relates to a control circuit for leading edge blanking time, and more particularly, to a control circuit for adjusting a leading edge blanking time and a power converting system including such a control circuit.
2. Description of the Prior Art
FIG. 1 is a diagram of a flyback converter 10 according to the prior art. A pulse-width modulation (PWM) control chip 100 outputs a PWM signal VPWM at an output pin OUT to control the turn-on and turn-off of a power switch 101 for transforming an input voltage Vin into an output voltage Vout. In order to prevent a large primary-side current lp of the flyback converter 10 from damaging elements, the PWM control chip 100 further detects a voltage level Vcs (Vcs=Rs×lp, which is generated by the primary-side current lp flowing through a sensing resistor Rs) at a current sensing pin CS. When the voltage level Vcs reaches a predetermined reference voltage level for over-current protection, the PWM control chip 100 enables an over-current protection mechanism. The output pin OUT stops outputting the PWM signal VPWM to turn off the power switch 101, which cuts off the primary-side current lp and thereby prevents the over-current phenomenon.
However, a spike is generated at the transient when turning on the power switch 101, which makes the voltage level Vcs detected by the current sensing pin CS rise immediately. Therefore, a fault trigger in the over-current protection mechanism of the PWM control chip 100 may happen. If the power switch 101 is wrongly turned off without an over-current phenomenon, the operations of the flyback converter 10 will be influenced. One solution is to add a leading edge blanking mechanism to the PWM control chip 100. The voltage signal Vcs detected by the current sensing pin CS is ignored (i.e., the over-current protection mechanism is not enabled) by the PWM control chip 100 within a leading edge blanking time, which begins at the moment when the power switch 101 is turned on.
Presently, most of the PWM control chips with current mode control have a built-in control circuit with a fixed leading edge blanking time. However, the control circuit with the fixed leading edge blanking time exhibits two disadvantages listed below:
When the power switch 101 is turned off, its drain voltage is Vd=Vin+(Vout/N)+lp×(Lk/Cd)1/2, wherein N is a turn ratio between the secondary-side winding and the primary-side winding of the transformer, Lk is a leakage inductor of the primary-side winding of the transformer, and Cd is the stray capacitor of the power switch 101. When the flyback converter 10 is turned on, a secondary-side current Is charges an output capacitor Co to increase the output voltage Vout from zero gradually. If the flyback converter 10 is at full load condition, the output voltage Vout will rise up slower. As can be known from the equation of Vout=L×(dls/dt), it's very difficult to fully release energy from the primary-side winding of the transformer T1 to the secondary-side winding of the transformer T1. Because the power switch 101 is turned on within the leading edge blanking time, the primary-side current lp accumulates a huge value if the fixed leading edge blanking time is too long. If the input voltage Vin of the flyback converter 10 is high, the excessively high drain voltage Vd of the power switch 101 may damage the power switch 101.
Most of the PWM control chips have a burst mode function. When the system is at light load condition, the PWM control chip 100 enters burst mode. At this time, if the voltage value of the feedback signal VCOMP of the PWM control chip 100 is smaller than a threshold level, the output pin OUT stops outputting the PWM signal VPWM. When the voltage value of the feedback signal VCOMP is greater than the threshold level, the system enters a normal current mode control and the output pin OUT starts to output the PWM signal VPWM, which makes the waveform of the feedback signal VCOMP a sine-wave-like pattern nearby the threshold level. When the PWM control chip 100 enters burst mode, the energy delivered from the input voltage Vin to the system may be smaller if the leading edge blanking time is too short. Therefore, the frequency of the sine-wave-like waveform of the feedback signal VCOMP gets higher, resulting in a higher switching loss and thus making the power-saving capability of the system poor.